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Description: 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
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Size: 7168 |
Author: 王立华 |
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Description: 8*8位的先入先出（fifo）数据缓冲器的vhdl源程序-8* 8 of the first-in-first out (FIFO) buffers the data source VHDL
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Size: 317440 |
Author: hailaing |
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Description: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
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Size: 30720 |
Author: 王晶 |
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Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
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Size: 378880 |
Author: lsg |
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Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
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Size: 10240 |
Author: David.Mr.Liu |
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Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
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Size: 228352 |
Author: 刘强 |
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Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
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Size: 46080 |
Author: 刘强 |
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Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
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Size: 4731904 |
Author: 李华 |
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Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC.
This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode.
Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput.
For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf"
Included: VHDL core, NIOS test application, PC test application
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Size: 6144 |
Author: 李涛 |
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Description: actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
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Size: 4096 |
Author: leo |
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Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
-----------------------------------------------------
dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to serial decoding
fifo.vhd FIFO megafunction intance
phase_register.vhd phase registers
-ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
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Size: 93184 |
Author: bin |
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Description: Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
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Size: 336896 |
Author: voldemortqq |
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Description: a fifo designed in vhdl. this fifo is implemented in a different way, using access type.
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Size: 2048 |
Author: mohandes |
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Description: FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
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Size: 1024 |
Author: duan |
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Description: fifo buffer in vhdl, first in first out in vhdl, vhdl code
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Size: 1024 |
Author: sgma |
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Description: Asynchronous FIFO Implementation in VHDL
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Size: 65536 |
Author: Mufossa |
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Description: it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
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Size: 1024 |
Author: Arash |
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Description: asynchronous fifo in vhdl
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Size: 2048 |
Author: spydeeps |
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Description: FIFO code implemented in VHDL.
FIFO is nothing but first in first out data buffer
Here i have implement it in VHDL
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Size: 67584 |
Author: sam |
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Description: vivado project file for fifo in vhdl
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Size: 19456 |
Author: sandeepthi |
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